Generally, one of the driving factors in the design of modern electronics is the amount of computing power and storage that can be shoehorned into a given space. The well-known Moore's law states that the number of transistors on a given device will roughly double every eighteen months. In order to compress more processing power into ever smaller packages, transistor sizes have been reduced to the point where the ability to further shrink transistor sizes has been limited by the physical properties of the materials and processes. Designers have attempted to overcome the limits of transistor size by packaging ever larger subsystems into one chip (systems on chip), or by reducing the distance between chips, and subsequent interconnect distance.
One method used to reduce the distance between various chips forming a system is to stack chips, with electrical interconnects running vertically. This can involve multiple substrate layers, with chips on the upper and lower surfaces of a substrate. One method for applying chips to the upper and lower side of a substrate is called “flip-chip” packaging, where a substrate has conductive vias disposed through the substrate to provide an electrical connection between the upper and lower surfaces.
Additionally, a package-on-package structure may be mounted on another carrier, package, PCB, or the like, via a solder ball grid array (BGA), land grid array (LGA), or the like. In some instances, the separation of the individual interconnections in an array, or bond pitch, may not match the die within the package-on-page structure, or may require a different connection arrangement than within the package-on-package structure.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. For clarity non-essential reference numbers are left out of individual figures where possible.